The present invention relates to a logic simulator for performing logic verifications of circuit models, such as logic gate circuits used in electronic apparatuses including data processing apparatuses.
One example of a logic simulator of this kind according to the prior art is disclosed in "Demand Driven Simulation: BACKSIM" by Steven P. Smith, M. Ray Mercer, Bishop Brock, in Proc. 24TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, pp. 181-187, May, 1987.
In this literature is disclosed the flow chart of event driven simulation performed with a conventional logic simulator.
The terminology used in this event driven simulation will be explained below by quoting from the literature cited.
"A signal connects a gate output to one or more gate inputs, which comprise the fanouts of the signal. The terms signal and output will be used interchangeably. Watched signals or outputs are saved during simulation for analysis by graphical or textual display tools after the run completes. Signal Watch commands specify that all changes to the specified signal during a simulation run are to be recorded for later analysis.
"Input stimuli are triplets, the constituent parts of which are a signal identifier, a new simulation value to be forced on the signal, and a time at which the specified signal is to take this new value. In event driven simulation, input stimuli initiate network activity, resulting in the propagation of changed signal values toward circuit outputs. Also in the event driven algorithm, the time queue is the mechanism by which signal changes that are to occur in the future are stored until it is time for them to be applied. Time queue events hold signal value changes pending on a specific output."
Next will be explained the event driven simulation performed with a conventional logic simulator with a quotation of some paragraphs and reference to FIG. 1 of this literature.
"Input to event driven simulators consists primarily of the circuit representation, input stimuli, and Signal Watch commands."
"Before commencing the main simulation loop, the input stimuli are scheduled into the simulator time queue. Once this task is complete, the main loop is entered, and simulation continues until, at the end of a pass, there are no simulation events remaining in the time queue for application in another iteration. At the top of the main loop, the time queue is examined to determine the earliest simulation time at which a signal change is scheduled. Within the main loop and after the time advance step, there are typically two sub loops: the update loop and the evaluation loop."
"The update loop of event driven simulation consists of three parts. First, an event that was scheduled to occur at the current simulation time (always maintained as a global variable) is removed from the time queue. Second, the specified signal is changed to the new value contained in the event record. And third, the output signal's fanout gates are placed in the evaluation stack to await evaluation in response to this input change. This process continues until there are no more events scheduled to occur at the current simulation time.
"The evaluation loop also consists of three parts. First, a gate identifier is popped off the evaluation stack. Second, the gate is evaluated to determine an output value given the gate's current input state. And third, if this newly calculated value is different from the value presently on the gate output, the change is scheduled into the time queue to occur after the gate's delay time expires. The evaluation loop proceeds until all gates in the stack have been evaluated.
"Of course, much subtlety associated with the implementation of an event driven simulator has been omitted in the interest of simplicity and brevity. However, the basic principles hold.
"In summary, computational effort is expended in event driven simulation as the direct result of changes on inputs to gates. Processing tends to move from gate inputs to outputs and then on to the fanout inputs driven by these outputs. Processing always proceeds monotonically forward in time."
However this logic simulator according to the prior art has the following disadvantages.
First, if any logical error is present in the logic circuit to be simulated, this logical error needs to be corrected to prepare a circuit model again, and this takes much time and manhours.
Second, since no state values can be set directly with respect to the internal elements of the logic circuit to be simulated, simulation cannot be continued, unless the circuit model is modified, in any logic circuit in a later stage than the one in which the logic error has occurred.